Metal-oxide-semiconductor ("MOS") electrically programmable read-only memories ("EPROMs") frequently use memory cells that have electrically isolated gates (floating gates). Information is stored in the memory cells in the form of charge on the floating gates.
One type of prior EPROM is the flash erasable and programmable read-only memory ("flash EPROM"). A typical flash EPROM has the same array configuration as a standard EPROM. The array is thus organized into rows and columns. Memory cells are placed at intersections of word lines and bit lines. Each word line is connected to the gates of a plurality of memory cells in one row. Each bit line is connected to the drains of a plurality of memory cells in one column. The sources of all the memory cells are connected to a common source line. The flash EPROM can be programmed by a user, and once programmed, the flash EPROM retains its data until erased. Once programmed, the entire contents of the flash EPROM can be erased by electrical erasure. A high erasing voltage is made available to the sources of all the cells in the flash EPROM simultaneously. This results in a full array erasure. The flash EPROM may then be reprogrammed with new data.
Electrically erasing floating gate flash EPROM cells typically gives rise to a serious problem, specifically undererasing and overerasing. During an erasure operation, some memory cells may not be completely erased, leaving those cells still in a programmed-like state. Conversely, too much charge may be removed from some other memory cells, making those cells "depletion-like."
One prior art solution to solving this problem is to verify that the floating gate of each of the memory cells in the flash EPROM is properly erased during the erasure operation. Typically, the high erasure voltage is pulsed such that the memory cells can be verified between the high erasure voltage pulses. When at least one of the memory cells has a very low threshold voltage, the erasure operation is terminated.
One disadvantage of the prior art solution is that such erasure and erasure verify cycle typically takes long time to finish the erasure operation. In order to prevent the memory cells from being over-erased, the width of the erasure voltage pulse needs to be small and the erasure verify sequence needs to be frequently and repeatedly applied between the erasure voltage pulses. This typically prolongs the erasure operation.
Another disadvantage is that the threshold voltage of each of the memory cells in the flash EPROM varies from memory cell to memory cell after the erasure operation. Due to various variations, such as temperature variation, process variation, and voltage supply variation, the memory cells typically cannot be erased to have a uniform threshold voltage. Typically, the threshold voltages of the memory cells range from 0.7 volts to 3 or 3.5 volts after each erasure operation. This typically affects the speed of the flash EPROM during the subsequent read operations. In addition, such flash EPROM cannot be used in a low power supply environment as a 3 volt power supply will not select an erased memory cell with a 3.5 volt threshold voltage during the read operation.
Moreover, as the flash EPROM experiences more and more program-erase cycles, the difference between the lowest threshold voltage and the highest threshold voltage in the flash EPROM after an erasure operation will increase accordingly. If the erasure sequence is set such that the erasure operation is terminated when any one of the memory cells within the flash EPROM reaches the predetermined lowest threshold voltage, then the flash EPROM will typically become unusable to the user after certain programming erasure cycles.